/*******************************************************************************
* @copyright: Shenzhen Hangshun Chip Technology R&D Co., Ltd
* @filename:  hk32c030xx_rcc.h
* @brief:     RCC initialization and configuration
* @author:    AE Team
*******************************************************************************/


/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HK32C030XX_RCC_H
#define __HK32C030XX_RCC_H

#ifdef __cplusplus
extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "hk32c030xx.h"


/** @addtogroup RCC RCC
  * @{
  */

/** @defgroup RCC_Exported_Types RCC_Exported_Types
  * @{
  */
typedef struct
{
    uint32_t SYSCLK_Frequency;
    uint32_t HCLK_Frequency;
    uint32_t PCLK_Frequency;
    uint32_t I2C1CLK_Frequency;
    uint32_t I2C2CLK_Frequency;
    uint32_t UART1CLK_Frequency;
    uint32_t UART2CLK_Frequency;
    uint32_t UART3CLK_Frequency;
    uint32_t RTCCLK_Frequency;
} RCC_ClocksTypeDef;
/**
  * @}
  */
/* Exported constants --------------------------------------------------------*/

/** @defgroup RCC_Exported_Constants RCC_Exported_Constants
  * @{
  */

/**
  * @brief  RCC_HSE_configuration
  */


#define RCC_HSE_OFF                      ((uint8_t)0x00)
#define RCC_HSE_ON                       ((uint8_t)0x01)
#define RCC_HSE_Bypass                   ((uint8_t)0x05)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                         ((HSE) == RCC_HSE_Bypass))


/**
  * @brief  RCC_PLL_Clock_Source
  */

#define RCC_PLLSource_HSI_Div2           ((uint8_t)0x00)
#define RCC_PLLSource_HSE                ((uint8_t)0x10)
#define RCC_PLLSource_HSI                ((uint8_t)0x11)

#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
                                   ((SOURCE) == RCC_PLLSource_HSI)      || \
                                   ((SOURCE) == RCC_PLLSource_HSE))




/**
  * @brief  RCC_PLL_Multiplication_Factor
  */


#define RCC_PLLMul_2                    ((uint32_t)0x00 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_3                    ((uint32_t)0x01 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_4                    ((uint32_t)0x02 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_5                    ((uint32_t)0x03 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_6                    ((uint32_t)0x04 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_7                    ((uint32_t)0x05 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_8                    ((uint32_t)0x06 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_9                    ((uint32_t)0x07 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_10                  ((uint32_t)0x08 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_11                   ((uint32_t)0x09 << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_12                   ((uint32_t)0x0A << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_13                   ((uint32_t)0x0B << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_14                   ((uint32_t)0x0C << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_15                   ((uint32_t)0x0D << RCC_CFGR_PLLMUL_Pos)
#define RCC_PLLMul_16                   ((uint32_t)0x0E << RCC_CFGR_PLLMUL_Pos)

#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
                             ((MUL) == RCC_PLLMul_16))



/**
  * @brief  RCC_PREDIV_division_factor
  */
#define  RCC_PREDIV_Div1               ((uint32_t)0x00 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div2               ((uint32_t)0x01 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div3               ((uint32_t)0x02 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div4               ((uint32_t)0x03 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div5               ((uint32_t)0x04 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div6               ((uint32_t)0x05 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div7               ((uint32_t)0x06 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div8               ((uint32_t)0x07 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div9               ((uint32_t)0x08 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div10              ((uint32_t)0x09 << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div11              ((uint32_t)0x0A << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div12              ((uint32_t)0x0B << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div13              ((uint32_t)0x0C << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div14              ((uint32_t)0x0D << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div15              ((uint32_t)0x0E << RCC_CFGR2_PREDIV_Pos)
#define  RCC_PREDIV_Div16              ((uint32_t)0x0F << RCC_CFGR2_PREDIV_Pos)

#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_Div1) || ((PREDIV) == RCC_PREDIV_Div2) || \
                                 ((PREDIV) == RCC_PREDIV_Div3) || ((PREDIV) == RCC_PREDIV_Div4) || \
                                 ((PREDIV) == RCC_PREDIV_Div5) || ((PREDIV) == RCC_PREDIV_Div6) || \
                                 ((PREDIV) == RCC_PREDIV_Div7) || ((PREDIV) == RCC_PREDIV_Div8) || \
                                 ((PREDIV) == RCC_PREDIV_Div9) || ((PREDIV) == RCC_PREDIV_Div10) || \
                                 ((PREDIV) == RCC_PREDIV_Div11) || ((PREDIV) == RCC_PREDIV_Div12) || \
                                 ((PREDIV) == RCC_PREDIV_Div13) || ((PREDIV) == RCC_PREDIV_Div14) || \
                                 ((PREDIV) == RCC_PREDIV_Div15) || ((PREDIV) == RCC_PREDIV_Div16))



/**
  * @brief RCC_System_Clock_Source
  */


#define RCC_SYSCLKSource_HSI            ((uint8_t)0x00)
#define RCC_SYSCLKSource_HSE            ((uint8_t)0x01)
#define RCC_SYSCLKSource_PLLCLK         ((uint8_t)0x02)
#define RCC_SYSCLKSource_LSE            ((uint8_t)0x10)
#define RCC_SYSCLKSource_LSI            ((uint8_t)0x11)
#define RCC_SYSCLKSource_HSI64         ((uint8_t)0x12)
#define RCC_SYSCLKSource_HSI16          ((uint8_t)0x13)
#define RCC_SYSCLKSource_EXTCLK         ((uint8_t)0x14)

#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK) || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSE)    || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSI64) || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSI16) || \
                                      ((SOURCE) == RCC_SYSCLKSource_EXTCLK))





/**
  * @brief RCC_AHB_Clock_Source
  */


#define RCC_SYSCLK_Div1                  ((uint32_t)0x00 << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div2                  ((uint32_t)0x08 << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div4                  ((uint32_t)0x09 << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div8                  ((uint32_t)0x0A << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div16                 ((uint32_t)0x0B << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div64                 ((uint32_t)0x0C << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div128                ((uint32_t)0x0D << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div256                ((uint32_t)0x0E << RCC_CFGR_HPRE_Pos)
#define RCC_SYSCLK_Div512                ((uint32_t)0x0F << RCC_CFGR_HPRE_Pos)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
                           ((HCLK) == RCC_SYSCLK_Div512))



/**
  * @brief RCC_APB_Clock_Source
  */


#define RCC_HCLK_Div1                    ((uint32_t)0x00)
#define RCC_HCLK_Div2                    ((uint32_t)0x04)
#define RCC_HCLK_Div4                    ((uint32_t)0x05)
#define RCC_HCLK_Div8                    ((uint32_t)0x06)
#define RCC_HCLK_Div16                   ((uint32_t)0x07)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
                           ((PCLK) == RCC_HCLK_Div16))


/**
  * @brief RCC_I2C_clock_source
  */

#define RCC_I2C1CLK_HSI                    ((uint8_t)0x00)
#define RCC_I2C1CLK_SYSCLK                 ((uint8_t)0x01)
#define RCC_I2C1CLK_PCLK                   ((uint8_t)0x11)

#define IS_RCC_I2C1CLK(I2C1CLK) (((I2C1CLK) == RCC_I2C1CLK_HSI)    ||  \
                                 ((I2C1CLK) == RCC_I2C1CLK_SYSCLK) || \
                                 ((I2C1CLK) == RCC_I2C1CLK_PCLK))


#define RCC_I2C2CLK_PCLK                   ((uint32_t)0x00000000)
#define RCC_I2C2CLK_HSI                    ((uint32_t)0x04000000)
#define RCC_I2C2CLK_SYSCLK                 ((uint32_t)0x08000000)

#define IS_RCC_I2C2CLK(I2C2CLK) (((I2C2CLK) == RCC_I2C2CLK_PCLK)    ||  \
                               ((I2C2CLK) == RCC_I2C2CLK_HSI) || \
                               ((I2C2CLK) == RCC_I2C2CLK_SYSCLK))




/**
  * @brief RCC_UART_clock_source
  */
#define RCC_UARTCLK_PCLK                  ((uint8_t)0x00)
#define RCC_UARTCLK_SYSCLK                ((uint8_t)0x01)
#define RCC_UARTCLK_LSE                   ((uint8_t)0x02)
#define RCC_UARTCLK_HSI                   ((uint8_t)0x03)

#define IS_RCC_UARTCLK(UARCLK) (((UARCLK) == RCC_UARTCLK_PCLK)   || \
                                   ((UARCLK) == RCC_UARTCLK_SYSCLK) || \
                                   ((UARCLK) == RCC_UARTCLK_LSE)    || \
                                   ((UARCLK) == RCC_UARTCLK_HSI))


/**
  * @brief RCC_Interrupt_Source
  */

#define RCC_IT_LSIRDY                    ((uint32_t)0x01)
#define RCC_IT_LSERDY                    ((uint32_t)0x02)
#define RCC_IT_HSIRDY                    ((uint32_t)0x04)
#define RCC_IT_HSERDY                    ((uint32_t)0x08)
#define RCC_IT_PLLRDY                    ((uint32_t)0x10)
#define RCC_IT_HSI16RDY                  ((uint32_t)0x20)
#define RCC_IT_CSSHSE                    ((uint32_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint32_t)0x80) == 0x00) && ((IT) != 0x00))

#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI16RDY) || \
                           ((IT) == RCC_IT_CSSHSE) )

#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)


/**
  * @brief RCC_LSE_Configuration
  */

#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
#define RCC_LSE_ON                       RCC_BDCR_LSEON
#define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
                         ((LSE) == RCC_LSE_Bypass))

/**
  * @brief RCC_RTC_Clock_Source
  */

#define RCC_RTCCLKSource_LSE             RCC_BDCR_RTC_SEL_0
#define RCC_RTCCLKSource_LSI             RCC_BDCR_RTC_SEL_1
#define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTC_SEL

#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))

/**
  * @brief RCC_LSE_Drive_Configuration
  */

#define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
#define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
#define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
#define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
                                 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
/**
  * @brief RCC_AHB_Peripherals
  */

#define RCC_AHBPeriph_GPIOF                ((uint32_t)0x00400000)
#define RCC_AHBPeriph_GPIOC                ((uint32_t)0x00080000)
#define RCC_AHBPeriph_GPIOB                ((uint32_t)0x00040000)
#define RCC_AHBPeriph_GPIOA                ((uint32_t)0x00020000)
#define RCC_AHBPeriph_CRC                  ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FLITF                ((uint32_t)0x00000010)
#define RCC_AHBPeriph_SRAM                 ((uint32_t)0x00000004)
#define RCC_AHBPeriph_DMA                  ((uint32_t)0x00000001)

#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFA1FFAA) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFFA1FFBE) == 0x00) && ((PERIPH) != 0x00))


/**
  * @brief RCC_APB2_Peripherals
  */

#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00000001)
#define RCC_APB2Periph_TEMPSEN           ((uint32_t)0x00000008)
#define RCC_APB2Periph_ADC               ((uint32_t)0x00000200)
#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
#define RCC_APB2Periph_UART1             ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
#define RCC_APB2Periph_DBGMCU            ((uint32_t)0x00400000)

#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0x00B8A506) == 0x00) && ((PERIPH) != 0x00))





/**
  * @brief RCC_AHB2_Peripherals
  */

#define RCC_AHB2Periph_DVSQ                  ((uint32_t)0x00000001)


#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))



/**
  * @brief RCC_APB1_Peripherals
  */

#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
#define RCC_APB1Periph_UART2             ((uint32_t)0x00020000)
#define RCC_APB1Periph_UART3             ((uint32_t)0x00040000)
#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)

#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xE099B6EC) == 0x00) && ((PERIPH) != 0x00))


/**
  * @brief RCC_MCO_Clock_Source
  */

#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
#define RCC_MCOSource_HSI16              ((uint8_t)0x01)
#define RCC_MCOSource_LSI                ((uint8_t)0x02)
#define RCC_MCOSource_LSE                ((uint8_t)0x03)
#define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
#define RCC_MCOSource_HSI                ((uint8_t)0x05)
#define RCC_MCOSource_HSE                ((uint8_t)0x06)
#define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)


#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI16)      || \
                                   ((SOURCE) == RCC_MCOSource_SYSCLK)  || ((SOURCE) == RCC_MCOSource_HSI)        || \
                                   ((SOURCE) == RCC_MCOSource_HSE)     || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
                                   ((SOURCE) == RCC_MCOSource_LSI)     || ((SOURCE) == RCC_MCOSource_LSE))

/**
  * @brief RCC_MCOPrescaler
  */

#define RCC_MCOPrescaler_1            ((uint32_t)0x00 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_2            ((uint32_t)0x01 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_4            ((uint32_t)0x02 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_8            ((uint32_t)0x03 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_16           ((uint32_t)0x04 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_32           ((uint32_t)0x05 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_64           ((uint32_t)0x06 << RCC_CFGR_MCOPRE_Pos)
#define RCC_MCOPrescaler_128          ((uint32_t)0x07 << RCC_CFGR_MCOPRE_Pos)

#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_2)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_4)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_8)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_16) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_32) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_64) || \
                                         ((PRESCALER) == RCC_MCOPrescaler_128))


/**
  * @brief RCC_Flag
  */
#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
#define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
#define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
#define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
#define RCC_FLAG_V15PWRRST               ((uint8_t)0x57)
#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
#define RCC_FLAG_HSI16RDY                ((uint8_t)0x61)
#define RCC_FLAG_HSI64RDY                ((uint8_t)0x87)

#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \
                           ((FLAG) == RCC_FLAG_PLLRDY)  || ((FLAG) == RCC_FLAG_LSERDY)  || \
                           ((FLAG) == RCC_FLAG_LSIRDY)  || ((FLAG) == RCC_FLAG_OBLRST)  || \
                           ((FLAG) == RCC_FLAG_PINRST)  || ((FLAG) == RCC_FLAG_PORRST)  || \
                           ((FLAG) == RCC_FLAG_SFTRST)  || ((FLAG) == RCC_FLAG_IWDGRST) || \
                           ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
                           ((FLAG) == RCC_FLAG_HSI16RDY)|| ((FLAG) == RCC_FLAG_HSI64RDY)||\
                           ((FLAG) == RCC_FLAG_V15PWRRST))

#define IS_CSS_THRESHOLD_Value(VALUE) ((VALUE) <= 0x7F)


/**
  * @}
  */


/** @defgroup RCC_Exported_Functions RCC_Exported_Functions
  * @{
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);

/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_HSITrimValue(uint8_t HSITrimValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_HSI16Cmd(FunctionalState NewState);
void RCC_LSEConfig(uint32_t RCC_LSE);
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_HSI64Cmd(FunctionalState NewState);
void RCC_PLLPREDIVConfig(uint32_t RCC_PREDIV_Div);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler);

/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLKConfig(uint32_t RCC_HCLK);

void RCC_I2C1CLKConfig(uint32_t RCC_I2CCLK);
void RCC_I2C2CLKConfig(uint32_t RCC_I2CCLK);
void RCC_UART1CLKConfig(uint32_t RCC_UARTCLK);
void RCC_UART2CLKConfig(uint32_t RCC_UARTCLK);
void RCC_UART3CLKConfig(uint32_t RCC_UARTCLK);

void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);

/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);

void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);

void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);

/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint32_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint32_t RCC_IT);
void RCC_ClearITPendingBit(uint32_t RCC_IT);
void RCC_CSSThresholdConfig(uint8_t CSS_THRESHOLD_Value);
#ifdef __cplusplus
}
#endif

#endif /*__HK32C030XX_RCC_H */
/**
  * @}
  */
/**
  * @}
  */



